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Exposition: Electronics Below 10 nm
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Electronics Below 10 nm
Authors: Konstantin Likharev, State University of New York, Stony Brook, NY 11794-3800
Uploaded by:
bci1
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- Comments:
- 42 pages, yr 2003, lectures
- Abstract:
- The lectures "review the prospects for the development and practical introduction of ultrasmall electron devices,
including nanoscale field-effect transistors (FETs) and single-electron transistors (SETs), as well as new concepts
for nanometer-scalable memory cells. Physics allows silicon FETs to be scaled down to >>3 nm gate length, but
below >>10 nm the devices are extremely sensitive to minute (sub-nanometer) fabrication spreads. This sensitivity
may send the fabrication facilities costs (high even now) skyrocketing, and lead to the end of the Moore Law some
time during the next decade. Lithographically defined SETs can hardly be a panacea, since the critical dimension
of such transistor (its single-electron island size) for the room temperature operation should be below >>1 nm."
Keywords: nanoelectronics, electron devices, memory cells, logic
http://pavel.physics.sunysb.edu/~likharev/personal/NanoGiga.pdf
- Rights:
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http://pavel.physics.sunysb.edu/~likharev/personal/NanoGiga.pdf
Open access
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Pending Errata and Addenda
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